1. Field of the Invention
The present invention relates to a recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory, and particularly to a recording/reproduction device which utilizes both of the error correcting ability of the semiconductor memory and the error correcting ability of the controller of the device. According to the present invention, the process can be simplified even in case the semiconductor memory of a device has a unit data size of erasure larger than the unit data size of processing by the device. The inventive recording/reproduction device is fairly reliable and is inexpensive.
2. Description of the Prior Art
A flash memory disk which is an example of recording/reproduction devices using non-volatile semiconductor memories is made up of flash memory chips, an interface chip, a microprocessor, etc. as shown in FIG. 1 of Japanese Patent Unexamined Publication No. H9-305497.
The flash memory chip is liable to have an increased error rate when the write operation exceeds a certain number of times, and therefore it relies on the error correcting function (inclusive of the error detecting function) of the interface chip or microprocessor to retain the reliability of the flash memory disk.
The flash memory chip is also often used as a discrete part. Therefore, the flash memory chip is designed to have an error correcting function by itself so that it has a certain level of reliability, as disclosed in Japanese Patent Unexamined Publication No. H3-5995.
It is known that a variable-length format scheme for a mass magnetic disk system uses a concatenated code to reduce redundant bytes of the error correction code so as to enhance the efficiency of error correction, as disclosed in Japanese Patent Unexamined Publications No. S59-165541, No. S62-73336 and No. H1-155721.
In case flash memory chips having an error correcting function are used for a system, such as a flash memory disk, which is required to be more reliable than the flash memory chips as discrete parts, it is necessary to include a controller having a high-grade error correcting function outside the flash memory chips. It is problematic however in that the use of the error correcting function of the flash memory chip make a miss-correction, resulting in a degraded reliability of the system as the whole, and therefore this error correcting function is not always useful.
For example, when flash memory chips having an error correcting function for dealing with 1-byte errors are used for a system which necessitates the correction of up to 3-byte errors, a controller capable of correcting 3-byte errors is included in the system. A 3-byte error arising in a flash memory chip can be corrected by the controller without using the error correcting function of the flash memory chips. If, on the other hand, correction of the error by the error correcting function of the flash memory chip is attempted, it occasionally make a miss-correction due to the error beyond its ability and convert the 3-byte error into a 4-byte error which is now beyond the ability of the error correcting function of the controller. Consequently, the system becomes incapable of correcting even 3-byte errors.
Nevertheless, leaving the error correcting function of the flash memory chip unused is problematic in that the system has a needlessly large circuit area and is needlessly expensive due to the unused function.
If it is attempted to design a system having a more reliable error correcting function by use of a flash memory chip with an error correcting function as core element, it will be necessary to take a design procedure as shown by the flowchart of FIG. 18A and the block diagram of flash memory chip of FIG. 18B, in which step 1501 removes the error correcting function block 1512 of the flash memory chip 1511, step 1502 redesigns the interface block for the flash memory chip 1511 to make a new flash memory 1513, and step 1503 designs a controller 1514 and an error correcting function block is included in the controller, and in consequence it will be problematic in an increased design work and a rising cost.
Devices of xe2x80x9cmemory stickxe2x80x9d and MMC (Multi-Media Card) have their flash memory chip 1513 and controller 1514 integrated in one chip in order to reduce the size and weight. However, designing these devices also necessitates the procedure shown in FIG. 18A, resulting in an increased design work and rising cost.
Devices of a portable terminal and MPEG camera using a flash memory card (memory card formed of flash memory chips) often adopt a 512-byte unit data size of processing. Whereas, the flash memory chip has a trend of larger unit data sizes of erasure, e.g., 1024 bytes and 2048 bytes, with the intention of reducing circuit scale and speeding up per-byte processing speed. In this case, the error correction code is processed in the large unit data size of erasure.
Accordingly, it is necessary to read out data of 1024 bytes or more which is the unit data size of erasure to check the error correction code at each readout of data of 512 bytes which is the unit data size of processing, and also to read out data of 1024 bytes or more to re-calculate the error correction code at each writing of 512-byte data, resulting in an intricate process.
A high-reliability error correcting function involves high-speed computation, which needs a high-performance controller, and therefore it is expensive. However, flash memory cards used for the portable recording/reproduction device, etc. are required to be inexpensive more than being reliable.
The present invention is intended to overcome the foregoing prior art deficiencies and facilitate the design of a one chip semiconductor memory system which uses a memory chip core element with its error correcting function being kept active.
An object of the present invention is to provide a recording/reproduction device which uses a semiconductor memory with an error correcting function as core element, and which utilizes the error correcting function of the semiconductor memory and yet is more reliable in error correction than the semiconductor memory, and provide a semiconductor memory and which are useful for the recording/reproduction device.
Another object of the present invention is to provide a semiconductor memory and a memory chip which can simplify the process even in the case of having a unit data size of erasure larger than the unit data size of processing of devices which use these parts.
Still another object of the present invention is to provide a recording/reproduction device which is fairly reliable and is inexpensive.
At a first viewpoint, the present invention resides in a recording/reproduction device comprising a controller section having a first error correction code generator which generates a first error correction code for data put in from the outside, and a first error corrector which implements the error detection and correction by using the first error correction code, and a semiconductor memory section having a second error correction code generator which generates a second error correction code for the first error correction code provided by the controller section, a memory which stores the data from the controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, the second error correction code being a BCH code in the same Galois field as the first error correction code and having a continuous root, the controller section implementing the error correction by using the error correction result provided by the second error corrector.
The present invention also resides in a recording/reproduction device comprising a controller section having an external interface which transacts data with the outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements the error detection and correction by using the first error correction code, and a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code in the same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by the controller section, a memory which stores the data from the controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, the controller section implementing the error correction by using the error correction result provided by the semiconductor memory section.
Furthermore, the present invention resides in a recording/reproduction device comprising a controller section having an external interface which transacts data with the outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements the error detection and correction by using the first error correction code, and a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH (Bose-Chaudhuri-Hocquenghem) code on the same Galois field as the first error correction code and has a continuous root, for the data provided by the controller section and a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, a memory which stores the data, the first error correction code check symbol and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, a correction information indicator which indicates information on whether or not the second error corrector has corrected the data, information of the intermediate error correcting computation and information of the detected error position and error value to the first error corrector, and a data sender which sends the data and first error correction code check symbol read out of the memory or the data corrected by the second error corrector and the first error correction code check symbol to the first error corrector, the first error corrector detecting an error by using the data and first error correction code check symbol provided by the data sender and, if the second error corrector has corrected the data, restoring the error-incorrected data by using the error position and error value and, if error is detected in the restored data and the first error correction code check symbol, implementing the error correction for the restored data by using the first error correction code check symbol and information of computation, and implementing the error detecting an error by using the first error correction code, or, if the second error corrector has failed in data correction, attempting the error correction for the error-incorrected data by using the first error correction code check symbol and information of computation and, if the error correction fails, attempting the error correction for the restored data or the error-incorrected data by using the first error correction code check symbol.
Furthermore, the present invention resides in a semiconductor memory comprising a second error correction code generator which generates a second error correction code, which is a BCH code in the same Galois field as a first error correction code and has a continuous root, for data and a first error correction code check symbol provided by a first error corrector, a memory which stores the data and first and second error correction code check symbols, a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, a correction information indicator which indicates information on whether or not the second error corrector has corrected the data and first error correction code check symbol, information of the intermediate error correcting computation and information of the detected error position and error value to the first error corrector, and a data sender which sends the data and first error correction code check symbol read out of the memory or the data corrected by the second error corrector and first error correction code check symbol to the first error corrector.
In the recording/reproduction device of the first viewpoint, when data is recorded on the device, the controller section generates the first error correction code check symbol, the semiconductor memory section generates the second error correction code check symbol, and the data and first and second error correction code check symbols are stored in the memory. When data is read out of the device, the semiconductor memory section implements the error detection and correction for the data and first error correction code check symbol read out of the memory by using the second error correction code check symbol, and delivers the data and first error correction code check symbol read out of the memory or the corrected data and first error correction code check symbol to the controller section. The controller section implements the error detection for the data provided by the semiconductor memory section by using the first error correction code check symbol and, (1) if error is detected and the semiconductor memory section has corrected the error, the controller section cancels the result of error correction made by the semiconductor memory section and restores the data and first error correction code check symbol read out of the memory. For this process, the semiconductor memory section indicates information on whether or not correction has been done and information of the error position and error value to the controller section. Consequently, even if the semiconductor memory section has made a faulty correction, the controller section is not adversely affected, but can correct the error based on its error correction ability. Otherwise, (2) if error is detected and the semiconductor memory section has not corrected the error, the controller section uses intact the data and first error correction code check symbol read out of the memory. In both cases of (1) and (2), the controller section implements the error correction by using the first and second error correction code. For this process, the semiconductor memory section indicates information on whether or not correction has been done and information of the intermediate error correcting computation to the controller section, and the first and second error correction codes are BCH codes on the same Galois field and have continuous roots, i.e., the first and second error correction codes have continuous xe2x80x9cpowerxe2x80x9d in the roots of their generation polynomials. Consequently, both error correcting abilities of the semiconductor memory section and controller section can be utilized to enhance the reliability.
The semiconductor memory section of the first viewpoint can be used suitably for the recording/reproduction device of the first viewpoint.
At a second viewpoint, the present invention resides in a recording/reproduction device comprising a controller section having an external interface which transacts data with the outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements the error detection and correction by using the first error correction code, and a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code on the same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by the controller section, a memory which stores the data from the controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, the controller section, upon detecting an error, implementing the error correction based on the first error correction code check symbol and information of computation provided by the semiconductor memory section, and, upon failing in error correction, implementing the error correction for the data read out of the memory by using the first error correction code check symbol.
Furthermore, the present invention resides in a recording/reproduction device comprising a controller section having an external interface which transacts data with the outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements the error detection and correction by using the first error correction code, and a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code on the same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by the controller section, a memory which stores the data, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, a detection/correction information indicator which indicates information on whether or not the second error corrector has detected an error, information on whether or not the data and first error correction code check symbol have been corrected and information of the intermediate error correcting computation to the first error corrector, and a data sender which sends the data and first error correction code check symbol read out of the memory and the data and first error correction code check symbol which are corrected by the second error corrector to the first error corrector, the first error corrector, in case the second error corrector has not detected an error but detected an error in the data read out of the memory by using the first error correction code check symbol, or in case the second error corrector has failed in data correction but detected an error in the data read out of the memory by using the first error correction code check symbol, or in case of detecting an error by using the first error correction code check symbol in the data which has been corrected by the second error corrector, attempting the error correction for the data read out of the memory by using the first error correction code check symbol and information of computation and, if error correction fails, attempting the error correction for the error-incorrected data read out of the memory by using the first error correction code check symbol.
Furthermore, the present invention resides in a semiconductor memory section comprising a second error correction code generator which generates a second error correction code, which is a BCH code on the same Galois field as the first error correction code and has a continuous root, for data and a first error correction code check symbol put in from the outside, a memory which stores the data and first and second correction code check symbols, a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, a detection/correction information indicator which indicates information on whether or not the second error corrector has detected an error, information on whether or not the data and first error correction code check symbol have been corrected and information of the intermediate error correcting computation to the first error corrector, and a data sender which sends the data and first error correction code check symbol read out of the memory and the data and the first error correction code check symbol corrected by the second error corrector to the first error corrector.
In the recording/reproduction device of the second viewpoint, when data is recorded on the device, the controller section generates the first error correction code check symbol, the semiconductor memory section generates the second error correction code check symbol, and the data and first and second error correction code check symbols are stored in the memory. When data is read out of the device, the semiconductor memory section implements the error detection and correction for the data and first error correction code check symbol read out of the memory by using the second error correction code check symbol, and delivers the data and first error correction code check symbol read out of the memory and the corrected data and first error correction code check symbol to the controller section. When the controller section, in case the second error corrector has not detected error but detected error in the data and first error correction code check symbol read out of the memory or in case the second error corrector has failed to correct the data and first error corrected code check symbol but has detected error in the data and first error correction code check symbol read out of the memory, attempts the error correction for the data read out of the memory by using the first error correction code check symbol and information of computation (for this process, semiconductor memory section indicates information on whether or not an error has been detected and information of the intermediate error correcting computation to the controller section, and the first and second error correction codes are BCH codes in the same Galois field and have continuous roots, i.e., the first and second error correction codes have continuous xe2x80x9cpowerxe2x80x9d in the roots of their generation polynomials) and, if the error correction fails, implements the error correction for the data read out of the memory by using the first error correction code check symbol. Consequently, both error correcting abilities of the semiconductor memory section and controller section can be utilized to enhance the reliability. In case the second error corrector has corrected the data but an error is detected in the error-corrected data by use of the error-corrected first error correction code check symbol, the controller section implements the error correction for the error-incorrected data read out of the memory by using the error-incorrected first error correction code check symbol and information of computation. For this process, the semiconductor memory section indicates information on whether or not an error has been detected and information of the intermediate error correcting computation to the controller section, and the first and second error correction codes are BCH codes in the same Galois field and have continuous roots, i.e., the first and second error correction codes have continuous xe2x80x9cpowerxe2x80x9d in the roots of their generation polynomials. If the error correction fails, the controller section implements the error correction for the error-incorrected data read out of the memory by using the error-incorrected first error correction code check symbol. Consequently, even if the semiconductor memory section has made a faulty correction, the device is not adversely affected by it, and both error correcting abilities of the semiconductor memory section and controller section can be utilized to enhance the reliability.
The semiconductor memory of the second viewpoint can be used suitably for the recording/reproduction device of the second viewpoint.
In regard to the BCH code, it is preferable to use particularly the RS (Reed Solomon) code.
The information of computation is preferably a residual polynomial which is the residue resulting from the division of the code polynomial of the second error correction code by the generation polynomial, or the syndrome resulting from the substitution of the root of the generation polynomial into the code polynomial of the second error correction code.
At a third viewpoint, the present invention resides in a semiconductor memory which performs the error correction-coding in the unit data size of processing and the data erasure in the unit size which is twice or more than the unit data size of processing.
The semiconductor memory of the third viewpoint performs the error correction-coding in the unit data size of processing, and therefore, for example, it does not need to check the error correction code by reading out the whole data of 1024 bytes or more, which is a unit data size of erasure, at every readout of data of 512 bytes which is a unit data size of processing, and it does not need to re-calculate the error correction code by reading out the whole data of 1024 bytes or more, which is the unit data size of erasure, at every rewriting of data of 512 bytes which is the unit data size of processing. Consequently, even in case the application device has a unit data size of erasure larger than the unit data size of processing, the process can be simplified. Having a unit data size of erasure twice or more than the unit data size of processing reduces the circuit scale and increases the per-byte processing speed.
At a fourth viewpoint, the present invention resides in a recording/reproduction device which incorporates a microprocessor having an interface function for data transaction with the outside and a semiconductor memory having an error correcting function.
The recording/reproduction device of the fourth viewpoint is inexpensive owing to the use of a microprocessor for the major component part, and is fairly reliable owing to the presence of the error correcting function in the semiconductor memory.
At a fifth viewpoint, the present invention resides in a memory card comprising a card controller section having a first error correction code generator which generates a first error correction code for data put in from the outside and a first error corrector which implements the error detection and correction by using the first error correction code, a semiconductor memory section having a second error correction code generator which generates a second error correction code for the data and first error correction code provided by the card controller section, a memory which stores the data from the card controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, and a connecting section which transacts data with an external device, the second error correction code being a BCH code in the same Galois field as the first error correction code and having a continuous root, the card controller section implementing the error correction by using the error correction result provided by the second error corrector.
The memory card of the fifth viewpoint achieves the same effectiveness as the recording/reproduction device of the first viewpoint.
At a sixth viewpoint, the present invention resides in a memory card comprising a card controller section having an external interface which transacts data with the outside, a first error correction code generator which generates a first error correction code for input data, and a first error corrector which implements the error detection and correction by using the first error correction code, a semiconductor memory section having a second error correction code generator which generates a second error correction code, which is a BCH code in the same Galois field as the first error correction code and has a continuous root, for the first error correction code provided by the card controller section, a memory which stores the data from the card controller section, a first error correction code check symbol which is the first error correction code, with the data being excluded therefrom, and a second error correction code check symbol which is the second error correction code, with the data and first error correction code check symbol being excluded therefrom, and a second error corrector which implements the error detection and correction by using the data and first and second error correction code check symbols read out of the memory, and a connecting section which transacts data with an external device, the card controller section, upon detecting an error, implementing the error correction based on the first error correction code check symbol and information of computation provided by the semiconductor memory section and, upon failing in error correction, implementing the error correction for the data read out of the memory by using the first error correction code check symbol.
The memory card of the sixth viewpoint achieves the same effectiveness as the recording/reproduction device of the second viewpoint.